1. Field of the Invention
The present invention relates generally to analog signal sampling circuits, and more specifically, to a switched-capacitor sample/hold having reduced amplifier slew-rate and settling time requirements.
2. Background of the Invention
Switched-capacitor sample/hold circuits are in common use today. Integrated circuits such as analog-to-digital (A/D) converters as well as voltage-to-frequency (V/F) converters, switched capacitor filters and other analog signal processing components often incorporate switched-capacitor circuits and in particular switched-capacitor sample/hold circuits to provide sampling and filtering circuits with controllable gain and circuit performance.
The simplest form of sample/hold circuit utilizes a single capacitor and a switch that samples the input signal onto the capacitor for a fixed interval. The capacitor is followed by a buffer amplifier that isolates subsequent stages. Improved switched-capacitor sample/hold circuits alternate the position of a single capacitor between an input signal terminal and a feedback position in the follower amplifier, providing a sampled state that is isolated from the input and has low droop in the hold phase. However, the simple alternating position sample/hold circuit requires that the amplifier transition from a zero state to a full value corresponding to the sampled signal at each sampling interval.
Improved versions of the simple alternating position sample/hold circuit have been developed that use a secondary holding capacitor to hold the previous output value at the amplifier during the sample state, but for high level input signals at input frequencies approaching half of the sampling rate (i.e., the Nyquist rate), the amplifier still must transition significantly from the sample state to the hold state, as the previous value has changed significantly from the last sample. The requirement on the amplifier to respond to steps in output voltage in all of the above-described circuits sets a minimum slew rate and settling time requirement for a particular accuracy in the sample/hold circuit. The slew rate and setting time of the amplifier are a source of error in the switched-capacitor sample/hold circuit. The slew rate and settling time are cost drivers for the amplifier, and within an integrated circuit can mean increased area and power dissipation and/or increased voltage requirements.
Another source of error in switched-capacitor circuits in general, and switched-capacitor sample/hold circuits in particular, is error due to charge injection. Charge injection occurs when the control input of a switch that couples an analog signal to the sampling or holding capacitor transitions and charge is transferred via capacitive coupling from the control input of the switch (typically the gate of a MOSFET) to the capacitor.
Non-linearity error is particularly pervasive in the input switches of sample/hold circuits, as the switch control signals are typically logic signals and as the sampled input voltage increases, the difference between the gate-to-source voltage of the switch transistors over the threshold voltage effectively decreases in a manner that is dependent on the input signal and thereby introduces non-linearities.
Therefore, it would be desirable to provide a sample/hold circuit having reduced amplifier settling time and slew-rate requirements and reduced error resulting from amplifier settling time and slew-rate. It would further be desirable to provide such sample/hold circuit that has reduced susceptibility to error due to charge injection and improved linearity.